The basic concepts as well as the structure of the
SSD is a storage device that uses a semiconductor (semiconductor flash memory) as a storage medium? and is realized using purely electronic circuits.
SSD hardware includes several major components: master control, flash memory, cache chip DRAM (optional, some SSDs may only SRAM, and not configured with DRAM), PCB (power supply chip, resistors, capacitors, etc.), interface (SATA, SAS, PCIe, etc.), the main body of which is a PCB
1.1 Main functions of the main control
(1) Responsible for the management of data reading and writing: the data reading and writing operations requested by the host are completed in the NAND flash memory, and the necessary buffering, sorting, and error correction are performed.
(2) Garbage collection: According to the characteristics of flash memory, the data cannot be directly overwritten, it needs to be erased and then rewritten, and the master control manages this process.
(3) Wear and tear equalization: the master needs to control the number of times each part of the flash memory is erased or written, so as to avoid damage to some of the flash blocks due to excessive erasure.
(4) Error Correction: I understand that there is ECC error correction, the main principle of which is to correct out the location where bit reversal occurs through Hamming code. Because most of the bit reversal can be solved by rebooting, ECC is basically used in server storage devices, such as memory and solid state. And the price is relatively more expensive than consumer-grade products.
(5) Firmware update: Many products have bugs or some deficiencies when using them, and firmware updates are used to improve or fix these problems.
(6) Encryption: ensuring data security
1.2 Flash memory
(1) Flash memory is a non-volatile memory. Non-volatile means that data is retained after a power failure. The memory cells of flash memory are arrays of floating gate transistors, and each memory cell can store one or more bits of data, such as the following types of cells:
SLC single-layer cell, MLC multilayer cell, TLC three-layer cell, QLC four-layer cell. The number of bits of data stored in these storage units increases sequentially, and the reliability and speed decreases sequentially with lower cost.
(2) Read and write characteristics: write data into the flash page, and then write data can not be directly overwritten, write speed is limited to erase speed.
protocol basis
The entire basic process of SSD storage is actually quite simple, with the data passing through a computer and other devicesphysical interfaceAt this point into the physical storage layer; then through the flash memory conversion layer, the physical information is converted into logical code, and recognized by the computer, the entire storage process is over. In the storage process, there are a series of protocols and commands to guide the relevant equipment to work, of whichcommand protocolIt plays the role of overall command and control, and thelogical protocolThen it acts in the logic layer.
Common consumer-grade command protocols, logical protocols, and noun pairing relationships under the physical interface banner.
|
physical interface |
logical protocol |
command protocol |
|
SATA |
AHCI |
ATA |
|
M.2/PCIe |
||
|
PCIe/U2 |
NVMe |
NVMe |
2.1 NVME Definitions and Roles
NVMe, known as Non-Volatile Memory Express, is a non-volatile memory-based transport specification that runs on the PCIE interface and is a standardized protocol that establishes the format of the communication commands between the Host and the SSD, as well as the process of executing the commands. The birth of NVME and the advantages of NVME are described in detail./s/nVF2LJlZzlQwWn6OI0cb-g
2.2 NVME Commands
NVME contains two types of commands:Admin Command，IO Command, Admin Command is used to manage and control the SSD, IO Command is used to transfer data between the SSD and the Host.
2.3 nvme command execution process
-
1. Host writes commands to the SQ:
The host (Host) generates a write command and writes it to the NVMe Submission Queue (SQ). This queue is located in the Host's memory, and multiple commands to be executed are stored in the queue. Each command has a descriptor that contains information such as the command type (e.g., read, write), destination address, and data length. -
2. Host writes DoorBell to notify the SSD of the fetch command:
After the host writes a command to the commit queue, it notifies the SSD controller that a new command has been placed in the queue by writing to the "DoorBell register". This register is similar to a "DoorBell" and is how the SSD controller receives notifications. -
3. The SSD receives a notification to take the command from the SQ:
When the SSD controller receives the notification from the host, it reads the commands in the commit queue. the SSD controller knows where to start reading commands because the host updates the "header pointer" of the queue to point to the most recently inserted command. -
4. SSD execution instructions:
The SSD controller parses the command and performs the appropriate action based on the type of command. For example, for a write command, the SSD writes the data provided by the host to the internal NAND flash memory. For a read command, the SSD reads data from the NAND flash and prepares to return it to the host. -
5. The SSD executes the instruction to completion and writes the execution result to the CQ:
When the SSD finishes executing a command, it writes the result to the Completion Queue (CQ), just like every time you write a function, the interface needs to have a return value.The CQ is also located in the host memory and is used to store the result of the execution of each command and the status information (e.g., success, failure, or error code). -
6. The SSD generates an interrupt to notify the Host that the execution of the command is complete:
After the SSD writes the result to the completion queue, it signals an interrupt to the host to notify it that the command has completed. This interrupt can be triggered in the form of a hardware interrupt to ensure that the host can respond in a timely manner. -
7. The Host receives the notification and begins processing the CQ to see the status and data returned when the command completes:
When the host receives an interrupt, it processes the entries in the completion queue to see the results of the execution of each command. This includes checking status codes to determine if the operation was successful and reading relevant data or error messages. -
8. Host writes DoorBell, notifies SSD that the execution result has been processed, and then releases the CQ:
When the host finishes processing the entries in the completion queue, it notifies the SSD controller again by writing to the DoorBell register to indicate that the completion queue entries have been processed and space can be freed up for subsequent command results. When the SSD controller receives this notification, it updates the queue's "tail pointer" to ensure that the next new results are written correctly.
Summary:
The entire process demonstrates the efficient communication mechanism between the host and SSD in the NVMe protocol, making full use of the parallel processing capabilities of the commit queue and completion queue to achieve high-speed, low-latency data reading and writing. At each step, the "DoorBell" register and interrupt mechanism ensures fast and synchronized coordination between the host and SSD. This process reminds me of the three handshakes and four waves of the http protocol.
Basic working principle
The operating system sends requests to the SSD, and the file system needs to convert these requests into commands that the SSD can recognize in order to perform the corresponding operations, just like a power adapter.The input of the SSD is commands, and the output is data and command status.The SSD front end receives the user's command requests, and after internal calculation and processing, outputs the data or status that the user needs. The front end of the SSD receives the user's command request, and after internal calculation and processing, outputs the data or status required by the user.
SSD system calls
3.1 SSD read and write
At the time of writing:
（1） The host sends a write command:The host (e.g., computer, server) sends write commands to the SSD through an interface (e.g., NVMe, SATA, etc.) with the data to be written. These commands are transmitted via a storage protocol (e.g., NVMe protocol).
（2）SSD receives commands and caches data: When an SSD receives a write command, it first temporarily stores the data in its internal RAM cache. This cache is a high-speed, low-latency storage area that can greatly increase data processing speed and avoid the latency associated with frequent flash write operations. (Cache systems are generally small, high-speed storage tools used to increase read and write speeds) In some cases, data may also be written directly to an SSD's SLC cache area, which takes advantage of the high write speed characteristics of SLC (Single-Level Cell) flash memory to further accelerate writes.
（3）FTL (Flash Translation Layer) Assigned Addresses: The FTL (Flash Translation Layer) is a key part of the SSD firmware. It is responsible for mapping the Logical Block Address (LBA) seen by the host to the actual physical flash address. Once the data is stored in the RAM cache, the FTL assigns a specific physical flash address to each logical block. Due to the nature of NAND flash, data cannot be overwritten, so the FTL also takes into account tasks such as Wear Leveling and Garbage Collection to ensure optimized storage life and performance.
（4）Data accumulation and writing to flash memory: When the data in the cache reaches a certain amount or certain conditions are triggered (e.g., the cache is full or a time threshold is reached), the FTL generates a write request ready to write the data to the actual NAND flash memory. This write request is sent to the back-end controller of the SSD, which writes the data in the cache to the corresponding NAND flash block based on the information in the request.
（5）NAND Flash Write: The back-end controller of the SSD writes data from the cache to the corresponding page of the NAND flash memory according to the physical address assigned by the FTL. Since NAND flash memory is written in pages and erased in blocks, this write process may involve complex page and block management operations. If the page to be written is in a new flash block, the write operation is relatively straightforward. However, if new data needs to be written in a block that is already in use, a garbage collection operation may be triggered to move and merge valid data to make room for the write.
（6）Write Completion and Confirmation: After the data is successfully written to the NAND flash memory, the SSD updates the corresponding mapping table and sends a write completion confirmation message to the host. After that, the data is permanently stored in the flash memory until it needs to be updated or deleted.
When reading: the host sends a read command, the SSD needs to map out the physical address of the data that needs to be read according to the logical address, so that the back-end transfers the data from the flash memory to the cache, and the front-end then returns this data to the host