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Mips single-cycle CPU design (logisim implementation)

Popularity：847 ℃/2024-10-29 11:34:07

Logisim single cycle cpu design document with thought questions

design documentation

Supported Instruction Sets

directives specification Description (RTL) machine code OPCODE/FUNCT
add add rd rs rt GPR[rd] <- GPR[rs]+GPR[rt] R-shape 0/100000
sub sub rd rs rt GPR[rd] <- GPR[rs]-GPR[rt] R-shape 0/100010
ori ori rt rs imme GPR[rt] <- GPR[rs] or imme type I 001101
lw lw rt offset(base) GPR[rt] <- memory[GPR[base]+offset] type I 100011
sw sw rt offset(base) memory[GPR[base]+offset] <- GPR[rt] type I 101011
beq beq rs rt offset if(GPR[rs]==GPR[rt]) PC <- PC+4+sign_extend(offset||00) type I 000100
lui lui rt imme GPR[rt] <- imme||0^16 type I 001111
jal jal target PC <- PC31..28||target||00 and GPR[31] <- PC + 4 J-type 000011
jr jr rs PC <- GPR[rs] R-shape 0/001000
sll sll rd rt s GPR[rd] <- GPR[rt] << s R-shape 0/000000
jalr jalr rd rs PC <- GPR[rs] , GPR[rd] <- PC+4 R-shape 0/001001
lb lb rt offset(rs) GPR[rt] <- memory[GPR[rs]+offset] type I 100000
sb sb rt offset(rs) memory[GPR[rs]+offset] <- GPR[rt] type I 101000
slt slt rd rs rt GPR[rd] <- (GPR[rs] < GPR[rt]) R-shape 0/101010
nop null No operation, vacant one cycle null 0x00000000

take note of：

  • included among thesesllThe command isR-commandThis is because we shift up to 31 bits and there is no need to save it in a 16-bit immediate number. Therefore, s is 5 bits, a special type R (only two registers are involved in the operation)
  • The nop doesn't need to perform any operations, but theStill need to do PC <- PC + 4,So when designing the NPCop don't forget that 2'b00 should also be able to be activated by the nop.

mips instruction set machine code supplement

R-command

opcode rs rt rd shamt funct
head of a unit 6 5 5 5 5 6
occupy a position 31-26 25-21 20-16 15-11 10-6 5-0

Type I commands

opcode rs rt immediate
head of a unit 6 5 5 16
occupy a position 31-26 25-21 20-16 15-0

J-command

opcode instr_index
head of a unit 6 26
occupy a position 31-26 25-0

Formal modeling of data pathways

Module Analysis

  • IFU(Instruction Fetch Unit)

Module Description

  • Internally, it includes PC (program counter), IM (instruction memory), and NPC (performs transfer address calculation for instructions).
  • The PC is implemented with registers and shall have an asynchronous reset function with the reset value as the start address.
  • Starting address: 0x00003000.
  • Address range: 0x00003000 ~ 0x00006FFF.
  • IM is implemented in ROM with a capacity of 4096 × 32 bits.
  • The starting address inside the ROM starts from 0, i.e., location 0 of the ROM stores the instructions with PC 0x00003000, and each instruction is a 32bit constant.
  • After the above analysis, it is easy to realize that the actual address width of the ROM is only 12 bits, so please use an appropriate method to relate the address stored in the PC to the IM.

Module Functions and Pin Definitions

  • PC: Asynchronous reset to address 0x0000_3000 when Reset=1
code orientations classifier for honorific people descriptive
CLK I 1 Single-cycle clock signals
Reset I 1 asynchronous reset (computing)
DI I 1 New command address from NPC
DO O 1 current command address
  • NPC: Calculate the address of the next instruction
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PC I 32 current command address
imm16 I 16 The address to jump to when beq
ZERO I 1 Whether the ALU subtraction result is 0
NPCop I 2 Decide what calculations NPCs should perform
NPC O 32 Address of the next instruction
  • IM: Read the command machine code and decompose it
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PC I 32 current command address
OPCODE O 6 OPCODE of the current instruction
rs O 5 rs number
rt O 5 rt number
rd O 5 rd number
imm16 O 16 immediate number
FUNCT O 6 FUNCT of the current instruction
  • GRF (register stack)

Module Description

  • Implemented with registers with write enable, the total number of registers is 32 and shall have asynchronous reset.
  • The value of register 0 is always kept at 0. All other registers are initially set to 0 (after reset) and do not require special setting.
  • Register 0 is a grounded design, so there are actually only 31 registers.

Module Functions and Pin Definitions

  • GRF: register heap used to store data in registers
code orientations classifier for honorific people descriptive
CLK I 1 clock signal
Reset I 1 Asynchronous reset signal
GRFWe I 1 Write Enable Signal
A1 I 5 rs register number
A2 I 5 rt register number
A3 I 5 rd register number
WD I 32 Write data to rd
RD1 O 32 rs register readout value
RD2 O 32 rt register readout value
  • ALU (Arithmetic Logic Unit)

Module Description

  • Provides 32-bit addition, subtraction, or operation and size comparison.
  • Addition and subtraction are treated as unsigned (no overflow is considered).

Module Functions and Pin Definitions

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A I 32 GPR[rs]
B I 32 GPR[rt] or Expanded Immediate Number
ALUop I 2 What operations are performed
RD O 32 algorithmic result
ZERO O 1 Whether the result is 0 when performing subtraction
  • Note: Specify that ALUop's 2'b00,2'b01,2'b10 denote the add, sub, and ori operations respectively
  • DM (data memory)

Module Description

  • Implemented using RAM with a capacity of 3072 × 32bit, it shall have an asynchronous reset function with a reset value of 0x00000000.
  • Starting address: 0x00000000.
  • Address range: 0x00000000 ~ 0x00002FFF.
  • The RAM should use dual port mode, i.e. set the Data Interface property of the RAM to Separate load and store ports.

Module Functions and Pin Definitions

code orientations classifier for honorific people descriptive
A I 32 Data memory address
DI I 32 Data written
We I 1 write enable
CLK I 1 Clock Signal, Asynchronous Reset
Reset I 1 reset signal
DO O 32 output
  • EXT (Expansion Unit)

Module Description

  • Use Logisim's built-in Bit Extender.
  • The effect is to expand immediate16 to 32bit.
  • Has the expansion selection signal EXTop.

Controller Modeling

  • Module Description
  • Control signals are constructed using an array of with or without gates.
  • As we can see from the analysis, what determines the control signal is which instruction is currently being executed, so we need to create a Boolean expression for each signal
  • With the array, we take each instruction as an output, and the boolean expression builds the method e.g., beq's opcode is 000100, then beq=!op[5]!op[4]!op[3]op[2]!op[1]*!op[0]
  • or array, it is only necessary to put the instruction or up that makes the control signal true.
  • Module Functions and Pin Definitions
code orientations classifier for honorific people descriptive Specific description of multi-bit control signals
OPCODE I 6 The opcode of the command
FUNCT I 6 Command funct
NPCop O 2 Decide what calculations NPCs should perform 2'b00 : +4
2'b01 : beq
2'b10 : jal
2'b11 : jr
WRSel O 2 GRF Write Address Source 2'b00 : rt
2'b01 : rd
2'b10 : ra(jal)
WDSel O 2 GRF write data sources 2'b00 : Output of ALU
2'b01 : DM output
2'b10 : Immediate
2'b11 : PC+4(jal)
EXTop O 2 How to Expand Immediate Numbers 2'b00 : unsigned extension
2'b01 : Signed extensions
2'b10 : Extend 16 zeros in the lower bits.
GRFWe O 1 GRF Write Enable
ALUop O 2 what kind of operation is performed 2'b00 : Addition
2'b01 : Subtraction
2'b10 : or operation
2'b11 : Left shift operation
BSel O 1 Whether the operator is immediate
DMWe O 1 DM Write Enable

topic of discussion

  1. Above, we introduced the basic method of understanding a single-cycle CPU through the FSM. Please point out which of the modules used in a single-cycle CPU performs the state storage function and which performs the state transfer function.

    echoThe single-cycle cpu involves the following modules: NPC, PC, IM, GRF, ALU, DM, which can be divided into two FSMs: the Moore-type FSM composed of NPC, PC, IM, which is called IFU, and the downstream mealy-type FSM composed of GRF, ALU, DM, respectively. in the IFU, the PC performs the state-storage function, and the NPC performs the state-transfer function; in the downstream FSM, the GRF performs the state-storage function; the entire IFU performs the state-transfer function. transfer function; in the downstream FSM, GRF plays the state storage function and the whole IFU plays the state transfer function.

  2. Now in our module we are using ROM for IM, RAM for DM and Register for GRF. Please analyze it and give us some suggestions to improve it.
    echoROM is read-only memory, it can only be read but not written, in the process of running the program, we have already translated the mips into machine code and imported it into IM's ROM, so there is no need to modify it, so it is reasonable, DM is the cpu's main memory, it will interact with the ALU and the GRF, so DM needs to have the function of reading and writing at the same time, so it is reasonable to use RAM, and the GRF is a temporary storage variable, which is consistent with the characteristics of registers, so it is reasonable. GRF is originally a register file, a temporary storage variable, which is in line with the characteristics of registers, so it is reasonable.

  3. Have you designed any other modules other than the ones hinted at above for the actual implementation? If so, please give an introduction and design ideas.
    echo: None.

  4. In fact, to implement the nop null instruction, we don't need to add it to the control signal truth table, why?
    echo: Since our controller is realized by with or array, the machine code of nop is 0x0000_0000, when nop is not considered, all the designed instruction outputs of controller with array are low, i.e., the cpu won't have any high level write enable, and the NPC also calculates the address of a single instruction in a normal way, at this point the circuit At this time, the circuit is vacant for one cycle, so there is no need to consider the design of the nop instruction.

  5. Read the test samples given in Pre's "MIPS Instruction Set and Assembly Language" section, evaluate their strength (in terms of coverage of individual instructions, coverage of various behaviors of a single instruction, etc.), and point out specific weaknesses.
    echo: I don't think it's strong enough. In terms of instruction set coverage there is a lack of testing for sub instructions, and also in terms of testing for specific single instructions, ori's data lacks testing for boundary cases such as immediate numbers of 0x0 or 0xffff; the add instruction lacks the case where the operation number contains 0x0; the test for the sw instruction is problematic: lw's offsets are not tested for the case where they are negative; lw and sw are the same problem; and the beq instruction's The problem is that it lacks the judgment and jump that the register is negative.

    Attached is the improved data for successfully self-testing out the GRF bug.
 # add sub ori lw sw beq lui nop
 ori $a0 $0 123#a0 = 123
 ori $a1 $a0 456#a1 = 507
 ori $a1 $a1 0#a1 = 507
 ori $a2 0xffff#a2 = 0xffff

 lui $a3 123#a3 = 0x007B_0000
 lui $t0 0xffff
 ori $t0 $t0 0xffff#t0 = 0xffffffff (-1)

 # wrong from here s0 is -1(wrong)
 add $s0 $a0 $a2#s0 = 65658
 add $s1 $a0 $t0#s1 = 122
 add $s2 $t0 $t0#s2 = -2
 add $s3 $0 $t0#s3 = -1

 sub $s4 $a0 $a1#s4 = -384
 sub $s5 $a1 $a0#s5 = 384
 sub $s6 $t0 $t0#s6 = 0
 sub $s7 $a0 $t0#s7 = 124


 ori $t1 0x0000#t1 = 0
 sw $a0 0($t1)#123
 sw $a2 4($t1)#0xffff
 sw $0 8($t1)#0
 sw $t0 12($t1)#-1
 ori $t2 20#t2 = 20
 sw $a1 -4($t2)#507

 ori $t3 $0 4
 lw $t4 4($t3)#t4 = 0xffff
 lw $t5 8($t3)#t5 = 0
 lw $t6 12($t3)#t6 = -1
 lw $t7 -4($t3)#t7 = 507

 beq $a0 $a1 loop1#unequal
 beq $s3 $t0 loop2#equal

 loop1:lw $t8 0($t1)
 loop2:lw $t8 4($t1)#t8 = 0xffff
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