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Lattice, Xilinx FPGA reg initialization assignment problem

Popularity：230 ℃/2024-11-08 16:40:30

I. Causes
Recently in the development of Lattice a low-power FPGA, encountered reg initialization reset problem, after searching for relevant information on the Internet is organized as follows;
II. How reg is initialized in FPGAs

  1. Initialized at definition time, e.g.
    reg r_test = 1'b1;
  2. In the reset statement, assign a value to reg, for example:
reg r_test;
always@(posedge sys_clk) begin
   if(~sys_rst_n) begin
       r_test <= 'b0;
   end
   else begin
       //logic
   end
end
  1. Initial statement initializes
    Many people think that initial statements can only be used in simulation and can't be synthesized, in fact initial statements can be synthesized (at least in vivado), for example:
reg r_test;
initial begin
   r_test = 'b0;
end

III. Issues
All the above three ways can successfully initialize reg in Xilinx FPGAs, but in Lattice's ICE5LP4K, the assignment method 1 seems to be different, such as the following code:

     reg             [15:0]              r_ADC_READ_NUM          = 16'd64        ;
    always @ (posedge SYS_CLK ) begin
        if( r_CMD_VALID)begin
            r_TX_BUF_RCNT	<= r_ADC_READ_NUM;
        end else if(r_TX_BUF_REN)begin
            r_TX_BUF_RCNT	<= r_TX_BUF_RCNT - 1'b1 ;
        end
        //  r_TX_BUF_RCNT_DONE	<= r_TX_BUF_RCNT == 10'd0? 1'b1 : 1'b0 ;

        r_TX_BUF_PRE	<= {r_TX_BUF_PRE[14:0] , r_CMD_VALID };
        r_TX_BUF_REN	<= r_QSPI_TN & (r_TX_BUF_PRE[13] | r_QSPI_OFF_SEL==4'd0 & s_QSPI_CLK_UP ) & r_TX_BUF_RCNT>0 ;// MCU READ 128 Byte once
    end

Although the r_ADC_READ_NUM register has been initialized by mode 1, r_TX_BUF_REN has not been able to be pulled up during the board test, and finally I had to suspect the value of r_TX_BUF_RCNT, which has been assigned to r_ADC_READ_NUM during r_CMD_VALID, and found that r_TX_BUF_RCNT has been 0, indicating that the system logic is running normally after reset initialization. _TX_BUF_RCNT was always 0, indicating that r_ADC_READ_NUM was not initialized, and after initializing it with a reset, the system logic operated normally:

always @(posedge SYS_CLK or negedge sys_nRst) begin
    if(~sys_nRst) begin
        r_ADC_READ_NUM <= 16'd64; // initial value: default 64
    end
    else begin
    end
end

IV. Summary
For xilinx FPGAs, assignment method 1 works fine and does not work in lattice, so to avoid this, it is recommended to adopt the reset assignment method to initialize reg to ensure that the data in reg is an initial value that we set after the FPGA is powered up.

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