Principles of Computer Composition and Operating Systems Chapter 2 Processor Composition and Management

Function and composition of the

1.1 The four main functions of the CPU

The 4 main functions of the CPU	descriptive
command and control	That is, the sequence control of the program. Program is a sequence of instructions, the mutual order of these instructions can not be arbitrarily reversed, must be strictly in accordance with the order of the program. Ensuring that the machine executes the program in sequence is the primary task of the CPU.
operational control	The function of an instruction is often realized by a combination of several operation signals. the CPU manages and generates the operation signals for each instruction taken out of memory, sends each operation signal to the corresponding component, and thus controls each component to perform the action required by the instruction.
time control	Timing of various operations is called time control. In the computer, the operation signals of various instructions are subject to the strict timing of time. The whole process of execution of an instruction is also subject to the strict timing of time, only in this way, the computer can work automatically in an organized manner.
data processing	That is, arithmetic and logical operations are performed on the data. Completing the processing of data is the fundamental task of the CPU.

1.2 Basic Components of CPU

subassemblies	Functional Description
controllers	A "decision-making body" that issues commands and coordinates and directs the operation of the entire computer system.
	- Removes an instruction from the instruction cache and indicates the location of the next instruction in the instruction cache.
	- The instructions are decoded or tested and the corresponding operation control signals are generated.
	- Directs and controls the direction of data flow between the CPU, data cache, and input/output devices.
operator (computing)	Data processing and handling components that perform arithmetic and logical operations.
	- Performs all arithmetic operations and produces results.
	- Performs all logical operations and performs logical tests such as a zero value test or a comparison of two values.
Cache	Cache memory to solve the speed mismatch between CPU and main memory.
register group	Temporary storage of computer words, including data buffer registers (DR), instruction registers (IR), program counter (PC), address registers (AR), and general purpose registers (Ro-R).
	- Data buffer register (DR): temporary storage of ALU operation results, or data words read from data memory, or external interface data words.
	- Instruction Register (IR): holds an instruction currently being executed.
	- Program Counter (PC): holds the address of the next instruction to be executed.
	- Address Register (AR): holds the address of the data cache memory cell currently being accessed by the CPU.
	- General Purpose Registers (Ro-R): provide the ALU with a workspace for arithmetic or logical operations.
Status Word Register (PSW)	Saves the condition code and system operating status information established by the operation or test result.
	- Saves the carry flag (C), overflow flag (V), zero flag (Z), negative flag (N), etc.

1.3 How an instruction runs inside the CPU

1. Take the finger:
   • First, according to the program counter (PC), the instruction is removed from theCommand cacheRemove it from theCommand Bus (IBUS)transfer toInstruction Register (IR)Center.
   • PC plus 1 points to the next instruction.
2. command decoding
   • commander-in-chief (military)Instruction Register (IR)hit the nail on the headOperator code (OP)is transferred to the command decoder and then passed through theOperation Controller, Timing GeneratorConverted to a control signal.
3. executable instruction
   ①The current instruction is a transfer instruction
   • Instruction Register IRThe address of the next instruction to be executed in the PC will be overwritten by the one to be added in the PC, and then the finger fetch operation will be performed.
     ②The current instruction is a non-transfer instruction
   • commander-in-chief (military)Instruction Register IRThe address code in theAddress Register ARand then from theIn the data cacheThe data is taken out and transferred via the data bus DBDS to theData buffer register DRThe data will be stored in thegeneral-purpose registerThe result of the calculation is transferred to theData buffer register DRThe state is transferred to theStatus Word Register PSWCenter.
     

2. Instruction system

2.1 Machine language and instructions

2.1.1 Basic concepts

nomenclature	define
machine language	A collection of machine instructions expressed in binary code that a computer can directly recognize and execute.
directives	A single CPU operation, defined by the instruction set architecture, is a command that instructs the computer to perform a certain operation.
instruction set	The entire collection of instructions that a computer can execute; all the functions of a computer that a computer programmer has access to.

2.1.2 Information that an instruction should generally contain

text	descriptive
Operation Code	Specifies the operation to be accomplished, such as ADD, I/O, etc. These binary codes are often called opcodes.
Address of the operand (Source Operand Reference)	The operation will involve one or more source operands, which are the inputs required for the operation.
Result Operand Reference	The operation may produce a result.
Next Instruction Reference	Tells the CPU where to fetch the next instruction after this one finishes executing.

The basic format of the command:Opcode | Address Code

2.1.3 Types and Functions of Instructions

Instruction type	Functional Description
data transmission instruction	Moving data from one place to another (actually "copying" it).
data operation instruction	Includes arithmetic and logical instructions.
shift command (computing)	Realize the left and right shift of the operand, divided into three kinds of arithmetic shift, logical shift and cyclic shift, can realize the left or right shift of the operand by one or several bits.
program control instruction	Instructions that control the flow of the program, including jump (conditional or unconditional) or branch instructions, subroutine call and subroutine return instructions, "soft interrupt" instructions, and stop instructions.

2.1.4 Addressing methods

addressing method	descriptive
direct addressing	Direct Addressing The effective address of the operand is given directly in the instruction word.
indirect addressing	Indirect Addressing The instruction specifies the address of the memory cell containing the operand address.
indirect register addressing
immediate-value addressing	The specified operand is not an address, but rather the data that is actually to be used
implicit addressing	does not explicitly indicate the operand, as a specific register is always used
Stack and stack operations	A storage structure with "last in, first out" access order
relative addressing	Add the current contents of program counter PC to the formal address given in the instruction to form the effective address of the operand.
variable address method (VAM)	Similar to relative addressing, but it adds the address provided by the instruction to the contents of the variable address register instead of the program counter.
base address	The effective address of an operand is equal to the sum of the formal address in the instruction and the contents of the base address register.

2.2 Design of Instruction Format

2.2.1 Basic concepts

The design of the instruction format consists of two aspects:

• Determines the length of the instruction;
• Divide the fields of the instruction, define the number of bits and meaning of each field
  instruction length
• Instruction word length: the number of bits of binary information contained in an instruction word.
  • Fixed-length instructions: all instructions in the instruction system have the same length.
  • Variable length instructions: the length of each instruction can be different.
• Machine word length: the number of bits of binary data that a computer can directly process

2.2.2 Types of instructions

Instruction type	specification	significance	Applicable models	clarification
zero address command (computing)	No operands required	Commands for empty operation, shutdown, etc.	common (use)	The operands are implicitly specified
I address instruction	A  OP (A) or AC  (AC) OP (A)	The result of the operation of operand A with opcode OP is stored back to A or AC	common (use)	The operands are implicitly specified
two-address instruction	A1  (A1) OP (A2)	Most commonly used command formats	Medium, small and micro	Available in several forms: S-S type, R-R type, R-S type
triple-address instruction	A3  (A1) OP (A2)	Often used for complex operations	Large and medium-sized machines	Example of formatting
multi-address instruction

2.2.3 Opcode types

Opcode Type	descriptive	vantage	Applicable models	typical example
fixed-length opcode	The opcode is fixed in length and centralized in one field of the command word	Simplifies hardware design and reduces instruction decoding time	Large, medium and super-small machines	not have
variable-length opcode	There are several different options for opcode length, adjusted to the number of addresses	Flexible for different command requirements	not have	not have
extended opcode	Efficiently shorten command word lengths while still meeting requirements	Reduced command word length for improved efficiency	not have	A machine instruction word is 16 bits long, with a fixed OP of 4 bits and three address codes of 4 bits each

2.2.4 Instruction Design

2.3 Instruction system

2.3.1 Basic Concepts of Instruction Systems

Instruction System Definitions

• The collection of all machine instructions in a computer.

The Importance of the Instruction System

• Directly affects the hardware architecture and system software.
• Affects the range of application of the machine.

Well-established command system requirements

• completeness: Sufficient commands are used directly, no software implementation is required.
• validity: The program runs efficiently.
• compatibility: The basic structure and instruction set are the same among the series machines, and the software is common.
• regularity: Consistent instruction format and data format, symmetry and homogeneity.

2.3.2 Instruction system design style

CISC (Complex Instruction System Computer)

• Enhanced command functionality and increased complexity.
• The instruction system is huge, up to 200-300 instructions.
• Multiple instruction formats and addressing methods.
• The timing of implementation and frequency of use varies widely.
• A microprogram controller is used.

RISC (Reduced Instruction System Computer)

• Streamline the command system and simplify functionality.
• Composed of simple commands that are used frequently.
• Fewer instructions, consistent length, fewer formats and addressing modes.
• Instruction pipeline scheduling with most instructions completed in one cycle.

2.3.2 Reasons for the emergence of RISC

The 2/8 rule

• 20% of the instructions take up 80% of the processor time and 80% of the infrequently used instructions take up 20% of the time.

3. Basic concepts of processes

3.1 Sequential execution characteristics of the program

hallmark	descriptive
sequential	The operation is carried out strictly in the order specified in the program.
encapsulation	The program runs in a closed environment, with exclusive access to all machine resources, and the state can only be changed by this program.
reproducibility	The environment and initial conditions are the same, and the result of multiple executions is the same, independent of the execution speed.

3.2 Concurrent execution characteristics of programs

hallmark	descriptive
intermittent	Programs share resources or collaborate on tasks, leading to an intermittent pattern of "execute-suspend-execute" activity.

3.3 The concept of process

define
A process is a single computational activity of concurrently executable programs on some collection of data, and is the basic unit of resource allocation and protection by the operating system.

3.4 Difference between a process and a program

distinguishing term	step	programs
Static/Dynamic	dynamic (science)	static (as in electrostatic force)
concurrency description	Can realistically describe concurrency	should not
life cycle	There are births and deaths, transient	relatively long
shelf life	One execution process, temporary	Can be stored for a long time
movement control unit	Separate unit for system allocation scheduling	Non-Movement Control Units
make up	Consists of both program and data	missing component
Create a process	Has the ability to create other processes	hasn't

3.5 Characterization of the process

hallmark	descriptive
dynamism	Has a dynamic address space that includes code, data, and system control information.
independent	The address spaces of the processes are independent of each other.
concurrency	Multiple process entities coexist in memory and can run simultaneously over time.
asynchronous	The processes move forward at their own independent and unpredictable pace.
structural	Includes program segments, data segments, and PCBs.

3.6 Types of processes

typology	descriptive
system process	Processes that play a role in resource management and control.
user process	Processes created for user arithmetic tasks.

3.7 Relationship between jobs and processes

Phase/State	descriptive
Submission Status	User programs and data waiting to be entered.
fallback	The job is entered on the backing memory and waits for scheduling.
execution status (computing)	The job enters memory and starts running until the calculation is complete.
completion state	Job calculations are completed until aftercare is completed and the system is exited.

3.8 Comparison of jobs and processes

comparison term	operation	step
mandated entity	A task entity to which a user submits a task to a computer.	The executing entity that accomplishes the user's tasks.
stockpile	The system places it in a job waiting queue in external memory waiting to be executed.	There is always a corresponding portion that exists in memory.
make up	A job may consist of multiple processes, at least one of them.	A single executing entity.
system application	Mainly used in batch systems.	Used in almost all multi-channel program systems.

4 The state of the process and its evolution

4.1 The three basic states of a process

State Type	descriptive	note
ready state (computing)	Runnable, has acquired the required resources except CPU, waiting for CPU allocation	Multiple processes in the ready state are arranged in a ready queue
running state (computing)	Running on the CPU; the number of processes in this state is less than or equal to the number of CPUs.	Automatically executes the system's idle process when no other process can be executed
blocked state (computing)	Waiting for some condition (such as an I/O operation or process synchronization) that prevents execution from continuing until the condition is met	Normally blocking processes are also organized into a blocking queue

4.2 Transition conditions for process states

state transition	prerequisite
Ready ->run	Scheduler selects a new process to run
Running ->Ready	- Running process runs out of time slice - Running process is interrupted because a high-priority process is in a ready state
Run-> wait	- OS has not yet completed services - Initialize I/O and must wait for results - Waiting for input from a process (IPC)
Waiting->ready	When the awaited event occurs
![[PCC2_12.png]]

4.3 Creation and termination states

state of affairs	descriptive	note
Create Status	The process has just been created and has not yet entered the ready queue	-
end state	The process has ended (normally or abnormally), has been removed from the ready queue, but has not yet been revoked	Holdover to allow other processes to gather information about the process

4.4 Suspend and Activate

manipulate	descriptive	rationale	goal	state transition
Suspend	The action of an operating system process manager to suspend a process in the foreground and transfer it to the background, i.e., to transfer the process out of memory into external memory.	As a result of the introduction of process prioritization, some low-priority processes may wait longer to be swapped to external memory	- Improvement of processor efficiency - Provide sufficient memory for running processes - For debugging	-Ready to hang:Active Ready to Quiet Ready -Blocking hangs: active blocking to static blocking -Row-to-Readiness Hangups: A Pair of Preemptive Time-Sharing Systems
Activate	Transferring a suspended process from the background to the foreground and resuming it from the point where it was suspended, i.e., transferring the process from external memory to memory			-Ready activation: static ready to active ready -Blocking activation: static blocking to active blocking

5. Process control blocks

5.1 Composition of process entities

constituent elements of a process entity	corresponds English -ity, -ism, -ization
program segment	Program code executed by the process
data segment	Data processed during the execution of the process
Process Control Block (PCB)	A data structure defined by the operating system to describe and manage a process, recording all the information required by the OS to describe the process and control its operation.

5.2 Role of PCBs

1. The OS controls and manages concurrently executing processes based on PCBs.
2. is the only indication of the existence of the process. Throughout the life cycle of a process, the system always controls the process through its PCB, i.e., the system perceives the existence of a process on the basis of its PCB.
3. When the OS wants to schedule a process, it looks up the current state and priority of the process from its PCB;
4. After scheduling to a process, it is necessary to set up the scene for resuming the process according to the processor status information stored in its PCB, and to find its program and data according to the memory start address of the program and data in its PCB;
5. Processes also need to access the PCB when they need to synchronize, communicate, or access files with processes with which they are cooperating during execution;
6. When a process suspends execution for some reason, it is necessary to save the handler environment of its breakpoints in the PCB.

5.3 Information in the process control block

PCBs are frequently accessed by the system, especially by process schedulers and dispatchers that run very frequently, and should therefore be memory-resident. System
Form a number of linked lists (or queues) of all PCBs and store them in a specially opened PCB area in the OS.

Information in the process control block: four pieces of information used to describe and control the operation of the process areProcess identification information, processor status
Information, process scheduling information and process control information。

Information in the process control block	corresponds English -ity, -ism, -ization	typology
Process identifier (name)	Uniquely identify a process	Internal Identifier. The operating system assigns each process a unique numeric identifier, usually the serial number of a process. It is primarily for system convenience. External identifier. Provided by the creator, it usually consists of letters, numbers, and often is used by the user (process) when accessing the process.
Processor status information	consists of the contents of the various registers of the processor. When the processor is running, much of the information is placed in the registers. When the processor is interrupted, all of this information must be saved in the PCB of the interrupted process so that when the process is re-executed, it can continue execution from the break point
Process scheduling information	Information related to process scheduling and process swapping	Process State: Indicates the current state of the process, which is used as a reference for process scheduling and swapping. Basis; Process Priority: An integer that describes the priority at which a process can use a processor, and processes with a higher priority should be given first access to the processor; Other information required for process scheduling: related to the process scheduling algorithm used, such as the total amount of time the process has been waiting for the CPU, the total amount of time the process has been executing, and so on. event: an event that is waiting to happen for a process to change from an execution state to a blocking state. i.e., the cause of the blockage
Process control information		Address of program and data: the place in memory or external memory where the program and data of the process are located ( address so that when the process is scheduled to execute again, it can find its program from the PCB and data; Process synchronization and communication mechanisms: mechanisms necessary to achieve process synchronization and process communication , such as message queue pointers, semaphores, etc., which may be placed wholly or partially in the In PCB; Resource list: A list of all the resources required by a process other than the CPU, and the resources that have been allocated to that process. A list of resources for the program; Link pointer: gives the next process in the queue that this process (PCB) is in The first address of the PCB.

5.4 Organization of process control blocks

Organization of process control blocks	descriptive
link method	Take PCBs with the same state and use the link word in them to Form a queue, thus forming a ready queue, a number of blocking queues idle queue
Indexing method	The system creates several index tables based on the status of all processes.

6. Process control

Responsibilities are to implement effective management of all processes in the system, including

• Creating a new process
• Termination of terminated processes
• Terminate a process that is unable to continue due to an event
• Responsible for process state transitions

6.1 Operating system kernel

Arrange the modules closely related to the hardware, modules that run more frequently and some common basic operations in the software level close to the hardware and resident in the memory, in order to improve the efficiency of the system operation.

Functions of the operating system kernel	corresponds English -ity, -ism, -ization
support function	Provides some of the basic functionality needed by many other modules in the OS. functions to support the work of these modules
Resource management functions	Process management, memory management, device management

6.2 Original language

• By a number of machine instructions, used to perform certain "atomic operation (atomic operation)" function of a process.
• The original language is indivisible and is not allowed to be interrupted during its execution, either by executing it from beginning to end or by not executing it at all.
• A common implementation of a proto-language is to provide the proto-language interface in the form of a system call, and the proto-language uses interrupt masking during execution to ensure that it cannot be interrupted.

6.3 Process Graph

is a directed tree used to describe the family relationships of a process, and the nodes in the tree represent the process

6.4 Process creation

6.4.1 Events that cause the creation of a process

event	descriptive
user login	When a legitimate user in a time-sharing system types a login command at a terminal, the system creates a process for the end user and inserts it into the ready queue.
Operation scheduling	In a batch system, when the job scheduler algorithmically schedules a job, it loads the job into memory, allocates the necessary resources for it, and immediately creates a process for it and inserts it into the ready queue.
Provision of services	When the running user program puts forward some kind of request, the system will create a process specifically to provide the services needed by the user, such as the request to print when the creation of a printing process
application request	All three of the above are created by the system kernel, the application process can also create its own process

6.4.2 Creation of Progress

Process creation can be done by calling the process creation primitivecreate() Follow the steps below to complete:

1. Request Free PCB：

   • Assigns a unique identifier to the new process and requests a free PCB from the PCB collection.

2. Allocating resources for new processes：

   • Allocate the necessary memory space for the program, data, and user stack of the new process.

3. Initialize the process control block：

   • Initialize identifier information
   • Initialize processor status information
   • Initialize processor control information

Process control block initialization contents

sports event	clarification
identifier information	Fill the new PCB with the system-assigned identifier and the identifier of the parent process.
Processor Status Information	The program counter points to the entry address of the program, and the stack pointer points to the top of the stack.
Processor control information	Sets the state of the process to ready, with a default priority of lowest priority

4. Insert the new process into the ready queue：
   • If the process ready queue is able to accept the new process, the new process is inserted into the ready queue.

6.5 Termination of processes

6.5.1 Events that cause a process to terminate (Termination)

1. Normal end：

   • In any computer system, there should be an indication that the process has finished running. For example, in a batch system, the Halt command is used; in a time-sharing system, the user utilizes Logs off.

2. Abnormal End:

   • Circumstances that force a process to terminate due to errors and failures, including but not limited to:

Exception End Type

typology	rationale
transborder error	The storage area accessed by the program has crossed the area of the process
conservation mistake	Process attempts to access an unallowed resource or file
illegal instruction	The program executes a non-existent instruction
Privilege directive error	The user process executes instructions that are only allowed to be executed by the OS
runtime	Process execution time exceeds the specified maximum
Wait for timeout	Waiting for an event longer than a specified maximum value
miscalculation in arithmetic operations	Performs forbidden operations, such as division by 0.
I/O Failure	An error occurred during the I/O process

3. outside interference：
   • Process termination due to operator or operating system, parent process request, parent process termination, etc.

6.5.2 Process termination

• OS calls the process termination primitiveterminate() to terminate the process, the procedure is as follows:
  1. Retrieves the PCB for the terminated process from the PCB collection based on the process's identifier.
  2. Determines the status of the terminated process:
     • If it is in a state of execution, it shall be terminated immediately.
     • If there are descendants, terminate all of them.

6.6 Blocking and Wake-up of Processes

6.6.1 Events that cause a process to block

1. Requesting system services：

   • The process requests the service, but the OS does not immediately fulfill it.

2. priming：

   • The process must complete the operation before execution can continue.

3. New data not yet available：

   • Data waiting between cooperating processes.

4. No new jobs available：

   • The system process completes its task and enters a blocking state.

6.6.2 Process Blocking

• The process is blocked by calling the blocking primitiveblock() Blocking itself. Blocking is an active behavior of the process itself.

6.7 Hanging and activation of processes

6.7.1 Hanging of processes

• When a user requests that a process be hung, the system uses the hang syntaxsuspend()。

How the suspend() principle works

1. Get the identifier of the pending process.
2. Check the status of the hung process.
3. Copies the PCB to the specified memory area.
4. If it is executing, turn to the scheduler.

6.7.2 Activation of processes

• When an activation event occurs, the system uses the activation primitiveactive() Perform activation.

The implementation of the active() principle

1. Calls the process from external memory into memory and checks the current state.
2. Decide how to handle the activation based on the status.
3. Perform scheduling comparisons and reschedule if necessary.

---