introductory
In order to execute an instruction, the CPU needs to recognize the instruction and find out what type of instruction is to be executed, how many cycles it takes, where the operand is, where the destination is, and other information, so that it can open the corresponding data path in the subsequent instruction execution process. The process of "recognizing instructions" is called decoding, and the mechanism that performs the instruction recognition function is called a decoder.
Two decoders
Because the 6502 CPU has a two-stage pipeline, there are two decoders, called the Pre-Decoder and the Post-Decoder. What is commonly referred to as the 6502 decoder is actually the Post-Decoder. The two decoders are located in the circuit diagram as shown below:
In the diagram, purple indicates the pre-decoder and blue indicates the post-decoder. I didn't include the decoder in the6502 The pre-decoder is found in the file, probably because the author didn't organize it.
The collaboration between the two decoders can be summarized from theHanson's Block Diagram Look out in the middle:
It can be seen that the pre-decoder is before the instruction register (IR) and the post-decoder is after the IR. The post decoder is responsible for decoding the instruction being executed, while the pre decoder simply decodes the instruction to be executed.
decoding principle
Both the pre-decoder and the post-decoder follow the same decoding principle, and observing their circuits, they both look like the following figure:
In the figure, the horizontal lines are the input lines and the vertical lines are the output lines. It is easy to see that the output of the decoder is actually a multi-input or non-logic. Since the non-logic can only recognize logic 1, the original data is usually inverted and added to the inputs in order to recognize logic 0. The bright green line in the above diagram is an inverse signal to the dark green line below it.
To illustrate the decoder principle, let's look at a simplified version of the decoder. The figure below shows a 4-in, 2-out decoder, which we will use as a model for illustration.
As mentioned earlier, the output is or non-logic. So\(A=\overline{\overline{X_0}+X_1+X_2+\overline{X_3}}\)which simplifies to\(A=X_0\overline{X_1}\overline{X_2}X_3\)The input pattern that can be recognized by A can be identified as1001The following is an example of how this can be recognized0x9The The same reasoning leads to\(B=\overline{X_1}X_2\)that is, the input patterns recognizable by B arex10x。
Pre-Decoder Inputs and Outputs
The pre-decoder is responsible for simple decoding of the instructions to be executed, so the decoding input is bus data. The bus data is stored temporarily in the pre-decoder register (PD) to avoid changes in the bus data from affecting the decoding result. Each clock cycle, the bus data is reloaded into the PD. The following figure shows the circuit diagram after the pre-decoder has been organized:
Applying the analytical method described earlier, the pre-decoder output can be obtained as follows:
| exports | Matching Mode | clarification |
|---|---|---|
| A | 1xx000x0 | LDX #, LDY #, CPX #, CPY # |
| B | xxx010x1 | Immediate number arithmetic instruction |
| C | xxxx10x0 | Implicit (Implied) Addressing Instructions |
| D | 0xx0xx0x | Stack operation instructions, flow control instructions, and arithmetic instructions |
After decoding, A, B, C, and D again follow the\(\overline{A+B+C\overline{D}}\) way to combine a new signal that indicates that the instruction is not a 2-cycle instruction.
Post Decoder Inputs and Outputs
The post decoder is responsible for decoding the instruction being executed, so the input data is the contents of the instruction register. In addition, its input contains the current clock cycle, so it can decode what type the current instruction is and how many cycles it is in.6502 The decoding results are labeled and will not be repeated in this article. There is a project on GitHub calledemu russia-has done a very thorough study of the 6502, which of course includes a study of the decoder. The interested reader is referred to theirresults-basedThe decoder outputs are described in detail inside.
postscript
The decoder of the 6502 occupies a large part of the chip, and is the core of instruction recognition. At a cursory glance, you may think that the decoder is very magical or complex, and I hope that the introduction of this article can help you get rid of the charm. If you think about it, you can actually think of the decoder as a read-only memory, except that it stores a very large number of 130 bits. It is for this reason that the 6502's decoder is sometimes called Decoder ROM.
To identify the commands corresponding to the input modes, I made a little tool:
If you cannot see the demo screen, you can clickhere (literary)Experience.
[Illustration]:
- Enter "xxxx10x0" and click "OK" to see all matching commands.
- The tool also supports expressions, for example, type "1xx000x0 || xxx010x1 || (xxxx10x0 && ~0xx0xx0x)" and click "OK" to see all the commands that satisfy the expression and then click "OK" to see all the commands that satisfy the expression.
consultation
- 6502
- 6502 Circuit Diagram
- EMU rassia - 6502 decoder
- 6502 decoder tool