Verilog implements 32-bit signed flow multiplier
1.4bit multiplication process
1. Unsigned X Unsigned Binary Multiplier
The following is the 4bit multiplier process (2X6)
0 0 0 0 0 0 1 0 (2)
X 0 0 0 0 0 1 1 0 (6)
---------------------
0 0 0 0 0 0 0 0 (0)
0 0 0 0 0 1 0 0 (4)
0 0 0 0 1 0 0 0 (8)
0 0 0 0 0 0 0 0 (0)
0 0 0 0 0 0 0 0 (0)
0 0 0 0 0 0 0 0 (0)
0 0 0 0 0 0 0 0 (0)
0 0 0 0 0 0 0 0 (0)
---------------------
0 0 0 0 1 1 0 0 (12)
2. Signed X signed binary multiplier
The following is the 4bit multiplier flow (-2 X-6)
1 1 1 1 1 1 1 0 (-2)
X 1 1 1 1 1 0 1 0 (-6)
---------------------
0 0 0 0 0 0 0 0
1 1 1 1 1 1 0 0
0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0
1 1 1 0 0 0 0 0
1 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
---------------------
0 0 0 0 1 1 0 0 (12)
3. Signed X unsigned binary multiplier
1 1 1 1 1 1 1 0 (-2)
X 0 0 0 0 0 1 1 0 (6)
---------------------
0 0 0 0 0 0 0 0
1 1 1 1 1 1 0 0
1 1 1 1 1 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
---------------------
1 1 1 1 0 1 0 0 (-12)
4. Unsigned X signed binary multiplier
0 0 0 0 0 0 1 0 (2)
X 1 1 1 1 1 0 1 0 (-6)
---------------------
0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
---------------------
1 1 1 1 0 1 0 0 (-12)
2. Process simplification
From the above four situations, we can summarize a rule that symbols do not affect the calculation process, but only affect the cutoff position.
For example, the unsigned X signed binary multiplier is as an example: bin(00000010) = dec(2), but for bin(11111010) treats it as a signed number as dec(-6), and as an unsigned as dec(250), that is, if the result of dec(2)*dec(250) is only taken 8 bits lower, it is bin(11110100) = dec(-12). Then I think that when calculating signed numbers multiplication, I just need to calculate it as an unsigned number, and finally control the cutoff position to calculate the signed calculator.
Then the following will simplify the 16bit multiplication to -1000 X -1200
1. Bit width expansion
dec(-1000) = bin(11111111111111111111110000011000) = dec(4294966296)
dec(-1200) = bin(11111111111111111111101101010000) = dec(4294966096)
2. Multiplier exponential decomposition
dec(4294966096) = 1*2^31 + 1*2^30 + 1*2^29 + 1*2^28 +
1*2^27 + 1*2^26 + 1*2^25 + 1*2^24 + 1*2^23 + 1*2^22 +
1*2^21 + 1*2^20 + 1*2^19 + 1*2^18 + 1*2^17 + 1*2^16 +
1*2^15 + 1*2^14 + 1*2^13 + 1*2^12 + 1*2^11 + 0*2^10 +
1*2^9 + 1*2^8 + 0*2^7 + 1*2^6 + 0*2^5 + 1*2^4 + 0*2^3 +
0*2^2 + 0*2^1 + 0*2^0
but:
dec(4294966296) * dec(4294966096) = dec(4294966296)*2^31 + dec(4294966296)*2^30 +
dec(4294966296)*2^29 + dec(4294966296)*2^28 + dec(4294966296)*2^27 +
dec(4294966296)*2^26 + dec(4294966296)*2^25 + dec(4294966296)*2^24 +
dec(4294966296)*2^23 + dec(4294966296)*2^22 + dec(4294966296)*2^21 +
dec(4294966296)*2^20 + dec(4294966296)*2^19 + dec(4294966296)*2^18 +
dec(4294966296)*2^17 + dec(4294966296)*2^16 + dec(4294966296)*2^15 +
dec(4294966296)*2^14 + dec(4294966296)*2^13 + dec(4294966296)*2^12 +
dec(4294966296)*2^11 + 0*2^10 + dec(4294966296)*2^9 + dec(4294966296)*2^8 +
0*2^7 + dec(4294966296)*2^6 + 0*2^5 + dec(4294966296)*2^4 + 0*2^3 +
0*2^2 + 0*2^1 + 0*2^0This formula looks a lot of complex, but if you think of the exponent as the left shift operator, then multiplication will be converted into left shift and addition.
3. Pipeline addition
Assumptionsnum = a + b + c + d + e + f + g + h, convert it into pipeline addition
4. Intercept on demand
dec(4294966296) * dec(4294966096) = hex(FFFF76800124F80)
Among them, the maximum bit width of 16 bits is 32 bits, and the next 32 bits are taken, that is,
hex(00124F80) = dec(1200000)A complete multiplication process is considered complete.
accomplish
16-bit signed multiplier code
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/28 22:54:41
// Design Name:
// Module Name: multiplier_16
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies: 16-bit signed multiplier
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module multipleer_16
#(
parameter A_WIDTH = 16,//Bit width of data A
parameter A_SIGNED = 1,//Is data A signed?
parameter B_WIDTH = 16,//Bit width of data B
parameter B_SIGNED = 1 //Is data B signed?
)
(
input clk ,
input rst,
input [A_WIDTH-1:0] A,
input [B_WIDTH-1:0] B,
output [A_WIDTH + B_WIDTH - 1:0] P
);
wire [32-1:0] C;
wire [32-1:0] D;
assign C = A_SIGNED?{{32-A_WIDTH{A[A_WIDTH-1]}},A}:{{32-A_WIDTH{1'b0}},A};
assign D = B_SIGNED?{{32-B_WIDTH{B[B_WIDTH-1]}},B}:{{32-B_WIDTH{1'b0}},B};
//*************************************************
genvar i0;
reg [31:0] sum0 [15:0];
generate
for (i0 = 0;i0<=15 ;i0=i0+1 ) begin
always @(posedge clk) begin
if(rst)begin
sum0[i0] <= 0;
end
else begin
case({D[2*i0+1],D[2*i0]})
2'b00:begin
sum0[i0] <= 0 << (2*i0);
end
2'b01:begin
sum0[i0] <= (0 + C) << (2*i0);
end
2'b10:begin
sum0[i0] <= ({C[30:0],1'b0} + 0) << (2*i0);
end
2'b11:begin
sum0[i0] <= ({C[30:0],1'b0} + C) << (2*i0);
end
endcase
end
end
end
endgenerate
genvar i1;
reg [31:0] sum1 [7:0];
generate
for (i1 = 0;i1<=7;i1=i1+1) begin
always @(posedge clk) begin
if(rst)begin
sum1[i1] <= 0;
end
else begin
sum1[i1] <= sum0[2*i1] + sum0[2*i1+1];
end
end
end
endgenerate
genvar i2;
reg [31:0] sum2 [3:0];
generate
for (i2 = 0;i2<=3 ;i2=i2+1 ) begin
always @(posedge clk) begin
if(rst)begin
sum2[i2] <= 0;
end
else begin
sum2[i2] <= sum1[2*i2] + sum1[2*i2+1];
end
end
end
endgenerate
genvar i3;
reg [31:0] sum3 [1:0];
generate
for (i3 = 0;i3<=1 ;i3=i3+1 ) begin
always @(posedge clk) begin
if(rst)begin
sum3[i3] <= 0;
end
else begin
sum3[i3] <= sum2[2*i3] + sum2[2*i3+1];
end
end
end
endgenerate
reg [31:0] sum4;
always @(posedge clk) begin
if(rst)begin
sum4 <= 0;
end
else begin
sum4 <= sum3[0] + sum3[1];
end
end
assign P = sum4;
endmodule32-bit signed multiplier code
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/09/11 22:21:12
// Design Name:
// Module Name: multiplier_pp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module multipler
#(
parameter A_WIDTH = 32,//Bit width of data A
parameter A_SIGNED = 1,//Is data A signed?
parameter B_WIDTH = 32,//Bit width of data B
parameter B_SIGNED = 1 //Is data B signed?
)
(
input clk ,
input rst,
input [A_WIDTH-1:0] A,
input [B_WIDTH-1:0] B,
output [A_WIDTH + B_WIDTH - 1:0] P
);
wire [64-1:0] C;
wire [64-1:0] D;
assign C = A_SIGNED?{{64-A_WIDTH{A[A_WIDTH-1]}},A}:{{64-A_WIDTH{1'b0}},A};
assign D = B_SIGNED?{{64-B_WIDTH{B[B_WIDTH-1]}},B}:{{64-B_WIDTH{1'b0}},B};
//*************************************************
genvar i0;
reg [63:0] sum0 [31:0];
generate
for (i0 = 0;i0<=31 ;i0=i0+1 ) begin
always @(posedge clk) begin
if(rst)begin
sum0[i0] <= 0;
end
else begin
case({D[2*i0+1],D[2*i0]})
2'b00:begin
sum0[i0] <= 0 << (2*i0);
end
2'b01:begin
sum0[i0] <= (0 + C) << (2*i0);
end
2'b10:begin
sum0[i0] <= ({C[62:0],1'b0} + 0) << (2*i0);
end
2'b11:begin
sum0[i0] <= ({C[62:0],1'b0} + C) << (2*i0);
end
endcase
end
end
end
endgenerate
genvar i1;
reg [63:0] sum1 [15:0];
generate
for (i1 = 0;i1<=15;i1=i1+1) begin
always @(posedge clk) begin
if(rst)begin
sum1[i1] <= 0;
end
else begin
sum1[i1] <= sum0[2*i1] + sum0[2*i1+1];
end
end
end
endgenerate
genvar i2;
reg [63:0] sum2 [7:0];
generate
for (i2 = 0;i2<=7;i2=i2+1 ) begin
always @(posedge clk) begin
if(rst)begin
sum2[i2] <= 0;
end
else begin
sum2[i2] <= sum1[2*i2] + sum1[2*i2+1];
end
end
end
endgenerate
genvar i3;
reg [63:0] sum3 [3:0];
generate
for (i3 = 0;i3<=3 ;i3=i3+1 ) begin
always @(posedge clk) begin
if(rst)begin
sum3[i3] <= 0;
end
else begin
sum3[i3] <= sum2[2*i3] + sum2[2*i3+1];
end
end
end
endgenerate
genvar i4;
reg [63:0] sum4 [1:0];
generate
for (i4 = 0;i4<=1 ;i4=i4+1 ) begin
always @(posedge clk) begin
if(rst)begin
sum4[i4] <= 0;
end
else begin
sum4[i4] <= sum3[2*i4] + sum3[2*i4+1];
end
end
end
endgenerate
reg [63:0] sum5;
always @(posedge clk) begin
if(rst)begin
sum5 <= 0;
end
else begin
sum5 <= sum4[0] + sum4[1];
end
end
assign P = sum5;
endmodule