Computer Architecture NUST Hu Weiwu Post-course Exercises Final Question Bank Key Selection Analysis Ⅰ (Chapters 2-3)

Chapter 2: Fundamentals of Computer System Architecture

first question

1. When running the same program P on three computers with different instruction systems, machine A needs to execute the$1.0×10^8$instructions, machine B needs to execute$2.0×10^8$instructions, the C machine needs to execute$4.0×10^8$instructions, but the actual execution times are all$10s$. Calculate the actual speed, in MIPS, of each of these 3 machines when running program P. Which of these 3 computers has the highest performance when running program P? Why?

Answers:

A is 10 MIPS, B is 20 MIPS, and C is 40 MIPS. all three machines have the same actual performance. The question asks about the performance when running program P.

Parsing:

First, we need to calculate the actual speed, in MIPS (millions of instructions per second), of each machine as it runs the program P.

MIPS is calculated as:

\[\text{MIPS} = \frac{\text{number of instructions}}{\text{execution time in seconds} \times 10^6} \]

For the A-machine:

Number of instructions:$1.0 \times 10^8$
Execution time: 10 seconds
MIPS value:

\[\text{MIPS}_A = \frac{1.0 \times 10^8}{10 \times 10^6} = 10 \, \text{MIPS} \]

For the B machine:

Number of instructions:$2.0 \times 10^8$
Execution time: 10 seconds
MIPS value:

\[\text{MIPS}_B = \frac{2.0 \times 10^8}{10 \times 10^6} = 20 \, \text{MIPS} \]

For the C machine:

Number of instructions:$4.0 \times 10^8$
Execution time: 10 seconds
MIPS value:

\[\text{MIPS}_C = \frac{4.0 \times 10^8}{10 \times 10^6} = 40 \, \text{MIPS} \]

Compare performance:

Although machine C has the highest MIPS value of 40 MIPS, the actual execution time for running program P is 10 seconds for all machines. Therefore, the actual performance of all three machines is the same when running program P.

Cause analysis:

Limitations of MIPS: The MIPS value reflects only the speed at which the machine executes instructions, but does not take into account the functional strength of each instruction and the differences in instruction sets. Different machines may need to execute different numbers of instructions to accomplish the same task.
program execution time: The real measure of program performance is execution time. Although the C machine has the highest MIPS value, since it needs to execute more instructions ($4.0 \times 10^8$bars), the final execution time is the same as the other machines.

Conclusion:

When running program P, the performance of the three machines is the same. This is because they take the same amount of time to complete the same task, i.e., 10 seconds.

fifth question

5. A processor is tested for power consumption, and the following data are obtained: the clock is not flipped, and the current is 500mA at a voltage of 1.05V; the clock frequency is 1GHz, and the current is 2500mA at a voltage of 1.1V. Calculate the static power consumption of this processor at 1.1V, and the total power consumption at 500MHz.

Answers:

At 1.1V, the processor's static power consumption is about 0.576W.
At 500MHz, the total power consumption of the processor is about 1.663W.

Parsing:

To calculate the static power consumption of the processor at 1.1V and the total power consumption at 500MHz, we need to decompose the total power consumption into static and dynamic power consumption and derive them using known data.

Step 1: Calculate total power consumption at 1.1V, 1GHz

The current is known to be 2.5A at 1.1V, 1GHz.

Total power consumption $ P_{\text{total_1GHz}} $:

\[P_{\text{total\_1GHz}} = V \times I = 1.1\,\text{V} \times 2.5\,\text{A} = 2.75\,\text{W} \]

Step 2: Estimate static power consumption at 1.1V

The current is known to be 0.5A when the clock is not flipped and 1.05V.

Static power consumption is at 1.05V:

\[P_{\text{static\_1.05V}} = V \times I = 1.05\,\text{V} \times 0.5\,\text{A} = 0.525\,\text{W} \]

The leakage current is assumed to be proportional to the square of the voltage (in general, the dependence of the leakage current on the voltage can be approximated as an exponential relationship, but for simplicity of computation, we use the square relationship).
Calculate the voltage scaling factor:

\[\left( \frac{1.1}{1.05} \right)^2 = \left(1.0476\right)^2 \approx 1.0975 \]

Therefore, the static power consumption is at 1.1V:

\[P_{\text{static\_1.1V}} = P_{\text{static\_1.05V}} \times 1.0975 = 0.525\,\text{W} \times 1.0975 \approx 0.576\,\text{W} \]

Step 3: Calculate dynamic power consumption at 1.1V, 1GHz

Dynamic power consumption $ P_{\text{dynamic_1GHz}} $:

\[P_{\text{dynamic\_1GHz}} = P_{\text{total\_1GHz}} - P_{\text{static\_1.1V}} = 2.75\,\text{W} - 0.576\,\text{W} = 2.174\,\text{W} \]

Step 4: Determine dynamic power consumption versus frequency

Dynamic power consumption is proportional to frequency, i.e:

\[P_{\text{dynamic}} \propto f \]

Step 5: Calculate dynamic power consumption at 500MHz

Calculate the frequency scale factor:

\[\frac{500\,\text{MHz}}{1\,\text{GHz}} = \frac{0.5\,\text{GHz}}{1\,\text{GHz}} = 0.5 \]
Thus, the dynamic power consumption is at 500 MHz:

\[P_{\text{dynamic\_500MHz}} = P_{\text{dynamic\_1GHz}} \times 0.5 = 2.174\,\text{W} \times 0.5 = 1.087\,\text{W} \]

Step 6: Calculate total power consumption at 500MHz

Total power consumption $ P_{\text{total_500MHz}} $:

\[P_{\text{total\_500MHz}} = P_{\text{static\_1.1V}} + P_{\text{dynamic\_500MHz}} = 0.576\,\text{W} + 1.087\,\text{W} = 1.663\,\text{W} \]

Summary:

Calculation of static power consumption: Using the current when the clock is not flipped, the static power consumption at the target voltage is calculated assuming that the leakage current is proportional to the voltage squared.
Calculation of dynamic power consumption: The dynamic power consumption is obtained by subtracting the static power consumption from the total power consumption, and the dynamic power consumption at different frequencies is calculated by utilizing the relationship that the dynamic power consumption is proportional to the frequency.
Calculation of total power consumption: Add the static and dynamic power consumption to get the total power consumption at a particular frequency.

Chapter 3 Binary and Logic Circuits

second question

2. Represent floating point numbers as follows.
(1) Convert single precision numbers to decimal numbers: 0x7ff0000,0xbe400000,0xff800000.
(2) Convert a double-precision number to a decimal number: 0x40350000000000000000,0x8008000000000000.
(3) Convert decimal numbers to single precision numbers: -100.0,0.25.
(4) Convert a decimal number to double precision: 1024.0,0.25.

reference answer：

Parsing:

This problem requires conversion between floating point and decimal numbers under the IEEE 754 standard. We will solve each sub-problem separately and explain each step in detail.

(1) Converts a single-precision floating-point number to a decimal number:

(a) 0x07FF0000

Step 1: Convert Hexadecimal Number to Binary Number

0x07FF0000 Converted to binary:

0    7    F    F    0    0    0    0
0000 0111 1111 1111 0000 0000 0000 0000

Step 2: Extract sign, exponent and mantissa bits

Sign Bit (S): 31st place.0(Positive)
Exponential (E): 30th to 23rd.00001111The conversion to decimal is15
Last digit (F):: 22nd to 0th.11110000000000000000000

Step 3: Calculate the ordinal code and the number of tails

Order code (e)：E - 127 = 15 - 127 = -112
Tail (M)：1 + (value corresponding to the last digit)

The value corresponding to the trailing digit:

\[Fraction=2−1+2−2+2−3+2−4=0.5+0.25+0.125+0.0625=0.9375\text{Fraction} = 2^{-1} + 2^{-2} + 2^{-3} + 2^{-4} = 0.5 + 0.25 + 0.125 + 0.0625 = 0.9375 \]

Therefore, M = 1 + 0.9375 = 1.9375M = 1 + 0.9375 = 1.9375

Step 4: Calculate the actual value

\[Value=(−1)S×M×2e=1×1.9375×2−112\text{Value} = (-1)^S \times M \times 2^e = 1 \times 1.9375 \times 2^{-112} \]

Since the exponent is small, the result is a positive number close to zero:

\[Value≈1.9375×2−112≈3.73×10−34\text{Value} \approx 1.9375 \times 2^{-112} \approx 3.73 \times 10^{-34} \]

Answers:

0x07FF0000 represents a decimal number of approximately$3.73×10−343.73 \times 10^{-34}$。

(b) 0xBE400000

Step 1: Convert Hexadecimal Number to Binary Number

B    E    4    0    0    0    0    0
1011 1110 0100 0000 0000 0000 0000 0000

Step 2: Extract sign, exponent and mantissa bits

Sign Bit (S)：1(Negative)
Exponential (E)：01111100and the decimal number is124
Last digit (F)：10000000000000000000000

Step 3: Calculate the ordinal code and the number of tails

Order code (e)：124 - 127 = -3
The value corresponding to the last digit：

\[Fraction=2−1=0.5\text{Fraction} = 2^{-1} = 0.5 \]

Therefore, M = 1 + 0.5 = 1.5M = 1 + 0.5 = 1.5

Step 4: Calculate the actual value

\[Value=(−1)1×1.5×2−3=−1.5×0.125=−0.1875\text{Value} = (-1)^1 \times 1.5 \times 2^{-3} = -1.5 \times 0.125 = -0.1875 \]

Answers:

0xBE400000 The decimal number represented is-0.1875。

(c) 0xFF800000

Step 1: Convert Hexadecimal Number to Binary Number

F    F    8    0    0    0    0    0
1111 1111 1000 0000 0000 0000 0000 0000

Step 2: Extract sign, exponent and mantissa bits

Sign Bit (S)：1(Negative)
Exponential (E)：11111111(all 1s)
Last digit (F)：10000000000000000000000(non-zero last digit)

Step 3: Judging Special Values

In the IEEE 754 standard, when the exponent bits are all ones and the trailing bit is zero, it means infinity; if the trailing bit is non-zero, it means NaN (not a number).

due to non-zero trailing digits:

Answers:

0xFF800000 indicates a value ofnegative infinity。

(2) Converts a double-precision floating-point number to a decimal number:

(a) 0x4035000000000000

Step 1: Convert Hexadecimal Number to Binary Number

4 0 3 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0100 0000 0011 0101 0000 ... (followed by all zeros)

Step 2: Extract sign, exponent and mantissa bits

Sign Bit (S)：0(Positive)
Exponential (E)：1000000011and the decimal number is1027
Last digit (F)：010100000...(only bits 51 and 48 are 1, the rest are 0)

Step 3: Calculate the ordinal code and the number of tails

Order code (e)：1027 - 1023 = 4
The value corresponding to the last digit：

\[Fraction=2−4+2−7=0.0625+0.0078125=0.0703125\text{Fraction} = 2^{-4} + 2^{-7} = 0.0625 + 0.0078125 = 0.0703125 \]

Therefore, M = 1 + 0.0703125 = 1.0703125M = 1 + 0.0703125 = 1.0703125

Step 4: Calculate the actual value

\[Value=1×1.0703125×24=1.0703125×16=17.125\text{Value} = 1 \times 1.0703125 \times 2^4 = 1.0703125 \times 16 = 17.125 \]

Notice that we miscalculated the tails; in fact, the 51st digit corresponds to 2-12^{{-1}, 48th position corresponds to 2-42}. But the 51st position in the title is0The 50th place is1, so the tail number actually is:

\[Fraction=2−2+2−4=0.25+0.0625=0.3125\text{Fraction} = 2^{-2} + 2^{-4} = 0.25 + 0.0625 = 0.3125 \]

Therefore, M = 1 + 0.3125 = 1.3125M = 1 + 0.3125 = 1.3125

Recalculate the actual value:

\[Value=1×1.3125×16=21\text{Value} = 1 \times 1.3125 \times 16 = 21 \]

Answers:

0x4035000000000000 The decimal number indicated is21.0。

(b) 0x8008000000000000

Step 1: Convert Hexadecimal Number to Binary Number

8 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1000 0000 0000 1000 0000 ... (followed by all zeros)

Step 2: Extract sign, exponent and mantissa bits

Sign Bit (S)：1(Negative)
Exponential (E)：00000000000(All zeros)
Last digit (F): The 51st position is1and the rest are0

Step 3: Calculate the actual value

Since the exponent bit is zero and the trailing bit is non-zero, this is aNon-normalized (subnormal)。

Order code (e)：1 - 1023 = -1022
The value corresponding to the last digit：

\[Fraction=2−12=0.000244140625\text{Fraction} = 2^{-12} = 0.000244140625 \]

Calculate the actual value:

\[Value=−1×0.000244140625×2−1022≈−1.1125369292536007×10−308\text{Value} = -1 \times 0.000244140625 \times 2^{-1022} \approx -1.1125369292536007 \times 10^{-308} \]

Answers:

0x8008000000000000 represents a decimal number of approximately−1.1125369×10−308-1.1125369 \times 10^{-308}。

(3) Converts a decimal number to a single precision floating point number:

(a) -100.0

Step 1: Determine the sign bit

Sign Bit (S)：1(Negative)

Step 2: Convert numbers to binary

100.0 The binary representation of1100100.0
Normalized to 1.100100 x 261.100100 \times 2^

Step 3: Calculate the index position

Order code (e)：6
Exponential (E)：e + 127 = 6 + 127 = 133
Exponential bit binary representation：10000101

Step 4: Calculate the trailing digit

Last digit (F)：10010000000000000000000(Fill decimal part to 23 digits)

Step 5: Combine bit strings and convert to hexadecimal

Bit String:

S |     E      |             F
1 | 10000101 | 10010000000000000000000

Convert to hexadecimal:

1 10000101 10010000000000000000000
= C2C80000

Answers:

The single-precision floating-point representation of -100.0 is0xC2C80000。

(b) 0.25

Step 1: Determine the sign bit

Sign Bit (S)：0(Positive)

Step 2: Convert numbers to binary

0.25 The binary representation of0.01
Normalized to: 1.0 x 2-21.0 \times 2^

Step 3: Calculate the index position

Order code (e)：-2
Exponential (E)：-2 + 127 = 125
Exponential bit binary representation：01111101

Step 4: Trailing digit

Last digit (F)：00000000000000000000000(because the fractional part is zero)

Step 5: Combine bit strings and convert to hexadecimal

Bit String:

S |     E      |             F
0 | 01111101 | 00000000000000000000000

Convert to hexadecimal:

0 01111101 00000000000000000000000
= 3E800000

Answers:

The single-precision floating-point representation of 0.25 is0x3E800000。

(4) Converts a decimal number to a double-precision floating-point number:

(a) 1024.0

Step 1: Determine the sign bit

Sign Bit (S)：0(Positive)

Step 2: Convert numbers to binary

1024.0 The binary representation of10000000000.0
Normalized to: 1.0 x 2101.0 \times 2^

Step 3: Calculate the index position

Order code (e)：10
Exponential (E)：10 + 1023 = 1033
Exponential bit binary representation：10000001001

Step 4: Trailing digit

Last digit (F)：000...0(52 digits, all zeros)

Step 5: Combine bit strings and convert to hexadecimal

Bit String:

S | E | F
0 | 10000001001 | 000.... .0 (52 bits total)

Convert to hexadecimal:

0 10000001001 000...0
= 4090000000000000

Answers:

The double-precision floating-point representation of 1024.0 is0x4090000000000000。

(b) 0.25

Step 1: Determine the sign bit

Sign Bit (S)：0(Positive)

Step 2: Convert numbers to binary

0.25 The binary representation of0.01
Normalized to: 1.0 x 2-21.0 \times 2^

Step 3: Calculate the index position

Order code (e)：-2
Exponential (E)：-2 + 1023 = 1021
Exponential bit binary representation：01111111101

Step 4: Trailing digit

Last digit (F)：000...0(52 digits, all zeros)

Step 5: Combine bit strings and convert to hexadecimal

Bit String:

S | E | F
0 | 01111111101 | 000.... .0 (52 bits total)

Convert to hexadecimal:

0 01111111101 000...0
= 3FD0000000000000

Answers:

The double-precision floating-point representation of 0.25 is0x3FD0000000000000。

Summary:

Single precision numbers are converted to decimal numbers:
- 0x07FF0000 ≈ $3.73×10−343.73 \times 10^{-34}$
- 0xBE400000 = -0.1875
- 0xFF800000 = Negative Infinity
Double precision numbers are converted to decimal numbers:
- 0x4035000000000000 = 21.0
- 0x8008000000000000 ≈ $−1.1125369×10−308-1.1125369 \times 10^{-308}$
Decimal numbers are converted to single precision floating point numbers:
- -100.0 = 0xC2C80000
- 0.25 = 0x3E800000
Decimal numbers are converted to double-precision floating point numbers:
- 1024.0 = 0x4090000000000000
- 0.25 = 0x3FD0000000000000

third question

3. Draw$e=a\&b|c\&d$The transistor stage circuit diagram of

Topic Analysis

The question asks to draw the circuit diagram of the transistor stage of the expression e=(a&b)∣(c&d)e = (a & b) | (c & d), while explanations and answers have been provided through pictures.

Logic expression simplification:

Original expression:

e=(a&b)∣(c&d)e = (a & b) | (c & d)
transformed into a non-gate realization:

e=∼(∼(a&b)&∼(c&d))e = \sim (\sim (a & b) & \sim (c & d))
According to the principles of logic circuit design, logic operations can be built through the P-tube (logic high) and N-tube (logic low) of CMOS, where:
- integration with: Realized by connecting the N-tubes in series.
- or door: Realized by connecting P-tubes in parallel.
- non-door (in grammar): Realized with a single-stage CMOS inverter.

Circuit Diagram Breakdown

Part I: (a&b)(a & b) and (c&d)(c & d)
- a&ba & b: adoptedN tubes in series respond in singingP-tubes in parallel Realization.
- c&dc & d: similarly adoptedN tubes in series cap (a poem)P-tubes in parallel Realization.
Part II: ∼(a&b)\sim (a & b) and ∼(c&d)\sim (c & d)
- Pass the output of the first part through a CMOS inverter for logic non-operation.
Third part: ∼(∼(a &b)& ∼(c &d))\sim (\sim (a & b) & \sim (c & d))
- For the two non-gate outputs of the second part, the outputs are passed through theN tubes in series cap (a poem)P-tubes in parallel Implementing Logic and Operations.
- Finally the result is inverted again by a CMOS inverter to get the final output.

point of attention

Logical design principles:
- The N tube is responsible for grounding and handling low levels.
- The P-tube is responsible for connecting to power and handling high levels.
- It cannot be reversed or the circuit will not work properly.
Circuit Realization Notes:
- The two-stage-and-non-gate circuit is implemented using a series-parallel structure of CMOS.
- The circuit needs to ensure drive capability at the output, so an inverter must be added to the last stage for buffering and logic adjustment.
Textbook Program:
- The first level realizes the logical non of (a&b)(a & b) and (c&d)(c & d).
- The second level realizes the output of the overall logical non
- Finally, the final result is obtained through an inverter.

summarize

The logic of e = (a&b)∣(c&d)e = (a & b) | (c & d) is realized by a two-stage-and-non gate circuit plus an inverter.
The circuit diagram is designed according to the CMOS principle, where the N and P tubes are paired to ensure logic functionality and reliability.
Note the function and connection requirements for series and parallel structures.

fourth question

4. Calculate aFO4The delay of the inverter is assumed to be 0.0036pF for the input capacitance, 0.0044pF for the average capacitance per load link, 0.023ns for the flip-flop delay, and 4.5ns for the delay per pF.

Reference Answer:

Title Resolution:

The question asks to calculate the delay of an FO4 and gives the inverter input capacitance, load link capacitance, flip-flop delay and other relevant parameters. The formulas and some of the derivations have been given in the reference answer, and are analyzed in detail below.

FO4 Definition of delay:

FO4 (Fan-Out of 4) is one of the most important parameters for measuring logic delay in digital circuits, and refers to the delay when one inverter drives 4 identical inverters. Its delay consists of the following two components:

Intrinsic Delay:
- The inverter's own delay, independent of the load.
- Given in this question$intrinsic delay = 0.023 ns\text{intrinsic delay} = 0.023 \, \text{ns}$。
Load Delay:
- Delay due to drive load capacitance.
- The load delay can be calculated using the following formula:$load delay = k ⋅ load capacitance ⋅ C\text{load delay} = k \cdot \text{load capacitance} \cdot C$
- where k is the unit load delay (per pF delay), in this problem$k=4.5 ns/pFk = 4.5 \, \text{ns/pF}$。

Known conditions:

Input capacitance of the inverter:$Cin=0.0036 pFC_{\text{in}} = 0.0036 \, \text{pF}$。
Average per load link capacitance:$Cwire=0.0044 pFC_{\text{wire}} = 0.0044 \, \text{pF}$。
This sign is delayed:$τintrinsic=0.023 ns\tau_{\text{intrinsic}} = 0.023 \, \text{ns}$。
Flip delay units:$k=4.5 ns/pFk = 4.5 \, \text{ns/pF}$。
$Fan-out = 4$。

Calculate the load delay:

The total load capacitance when the inverter drives 4 identical inverters is:

\[Ctotal=4⋅(Cin+Cwire)C_{\text{total}} = 4 \cdot (C_{\text{in}} + C_{\text{wire}}) \]

Substitute known values:

\[Ctotal=4⋅(0.0036+0.0044)=4⋅0.008=0.032 pFC_{\text{total}} = 4 \cdot (0.0036 + 0.0044) = 4 \cdot 0.008 = 0.032 \, \text{pF} \]

The load delay is:

\[τload=k⋅Ctotal=4.5⋅0.032=0.144 ns\tau_{\text{load}} = k \cdot C_{\text{total}} = 4.5 \cdot 0.032 = 0.144 \, \text{ns} \]

Calculate the FO4 total delay:

The total delay is:

\[τFO4=τintrinsic+τload\tau_{\text{FO4}} = \tau_{\text{intrinsic}} + \tau_{\text{load}} \]

Substitute known values:

\[τFO4=0.023+0.144=0.167 ns\tau_{\text{FO4}} = 0.023 + 0.144 = 0.167 \, \text{ns} \]

Summary:

FO4 Latency = 0.167 ns
The calculation of this question is consistent with the reference answer, which specifies the two sources of FO4 delay, i.e., intrinsic delay and load delay.
If the definition of FO4 changes in the title (e.g., driving multiple inverters or adjusting the way the load is calculated), the equation needs to be corrected according to the definition.

fifth question

5. Analyze the build-up time, hold-up time, and CLK→Q delay of the CMOS EDFF flip-flop (edge-triggered CMOS D-flip-flop) of Figure 3.1. Assuming that the delay of the inverter is 1ns, the delay of the transmission gate from the source to the drain (or from the drain to the source) is 0.5ns, and the delay of the transmission gate from the gate to the drain (or the source) is 0.75ns, the effect of the inverter delay due to the FIGHT of the LATCH is not taken into account.

Reference Answer:

Title Resolution:

Analyze the CMOS EDFF edge-triggered D-trigger of Figure 3.1 to find the following three parameters:

Establishment time$T_{\text{setup}}$
Holding time$T_{\text{hold}}$
Clock to Q delay$T_{\text{CK→Q}}$

Description of basic parameters:

Inverter Delay: $1 ns$
Transmission gate delay:
- Delay from gate to drain/source:$0.75 ns$
- Delay from drain to source:$0.5 ns$
Clock signal propagation delay:
- $T_{\text{CK→C}} = 2 \, \text{ns}$
- $T_{\text{CK→CN}} = 2 \, \text{ns}$(assuming consistent latency)

The parsing process:

1. Establishment time$T_{\text{setup}}$

Establishment time is defined as the arrival of the clock signal at$CK$ The time at which the internal state of the trigger must have completed changing and stabilized before the
A path is required for the data to travel from the D terminal to the 1N1 node inside the trigger:

\[D → N0 → N1 → N2 → N1 \]

D → N0 → N1 delay:

\[1 ns (inverter) + 0.5 ns (transmission gate) = 1.5 ns \]
N1 → N2 → N1 delay (state change within the loop):

\[1 ns+1 ns=2 ns \]

In addition, the delay in the propagation of the clock signal to the control side of the transmission gate has to be taken into account:

Take the minimum value:$min⁡(T_{CK→C},T_{CK→CN)}=min⁡(2,2)=2 ns$

Also add the gate-to-drain/source delay of the transmission gate:$0.75 ns$

Synthesize build time:

\[T_{setup}=1.5 ns+2 ns+2 ns+0.75 ns−2 ns=0.75 ns \]

2. Holding time$T_{\text{hold}}$

The hold time is defined as the minimum time that data DD must remain stable after the clock signal reaches CKCK.
The key is that the transmission gate N0N0 needs to be completely closed when the clock signal arrives to ensure that data DD no longer enters node N1N1.

The delay in the propagation of the clock signal to the control side of the transmission gate:

Take the maximum value:$\max(T_{\text{CK→C}}, T_{\text{CK→CN}}) = \max(2, 2) = 2 \, \text{ns}$
plus the gate-to-drain/source delay of the transmission gate:$0.75 ns$
Data D → N0 → N1D → N0 → N1 path delay:$1 ns+0.5 ns=1.5 ns$

Comprehensive calculation of hold time:

\[T_{\text{hold}} = 2 \, \text{ns} + 0.75 \, \text{ns} - 1.5 \, \text{ns} = 1.25 \, \text{ns} \]

3. Clock to Q delay$T_{\text{CK→Q}}$

The clock-to-Q delay is defined as the amount of time after the falling edge of the clock arrives that the Q output reflects the state of the flip-flop.
Data is passed from N2 → N3 → N4 → Q, and the delay of the clock-controlled transmission gate needs to be taken into account.

N2 → N3 → N4 → Q with delay:

\[0.5 ns+1 ns+1 ns=2.5 \text{ns} \]
The delay in the propagation of the clock signal to the control side of the transmission gate:

Take the maximum value:$\max(T_{\text{CK→C}}, T_{\text{CK→CN}}) = 2 \, \text{ns}$
plus the gate-to-drain/source delay of the transmission gate:$0.75 \, \text{ns}$

Synthesize the clock-to-Q delay:

\[T_{\text{CK→Q}} = 2 \, \text{ns} + 0.75 \, \text{ns} + 2.5 \, \text{ns} = 5.25 \, \text{ns} \]

Final Answer:

Establishment time:$T_{\text{setup}} = 0.75 \, \text{ns}$
Holding time:$T_{\text{hold}} = 1.25 \, \text{ns}$
Clock to Q delay:$T_{\text{CK→Q}} = 5.25 \, \text{ns}$

bibliography

[1] Computer Architecture Answers by Hu Weiwu from NUST (latest version) from CSDN.

[2] Computer Architecture 2nd Edition Hu Weiwu Tsinghua University Press